============================================================== Guild: wafer.space Community Channel: ℹ️ - Information / general Topic: Welcome to [wafer.space](https://wafer.space/) - documentation at [wafer.space github](https://github.com/wafer-space) - buy at [buy.wafer.space](https://buy.wafer.space) - archives at [discord.wafer.space](https://discord.wafer.space/) After: 2026-10-31 11:59 p.m. Before: 2026-12-01 12:00 a.m. ============================================================== [2026-11-01 12:36 a.m.] mithro_ NextPCB is likely the first [2026-11-01 12:53 a.m.] mithro_ I think I saw from the shipping address you where in Sydney? I know a bunch of ASIC people in Sydney and UNSW has bought a slot on Run #3. I can do the introduction. [2026-11-01 12:54 a.m.] tholin Ah damn. I go on a short vacation or sorts starting on the 17th, so I’ll miss the initial COB shipment and my bring-ups will be delayed. [2026-11-01 2:27 a.m.] sudonet Started a thread. [2026-11-01 7:47 a.m.] 246tnt Ok, I saw pcbcart had just put a COB related blog post ( https://www.pcbcart.com/article/content/cob-wire-bonding-sensors.html ) so I thought this was related. {Embed} https://www.pcbcart.com/article/content/cob-wire-bonding-sensors.html Chip-on-Board (COB) & Wire Bonding Assembly for High-Reliability Se... COB and wire bonding for sensor modules: bond selection, pull/shear tests, glob top, and DFM tips. [2026-11-01 10:29 a.m.] mithro_ @stuart -^ [2026-11-01 10:41 a.m.] namibj I uploaded a thing.... https://github.com/namibj/BondTest72-Programmable-LDO {Embed} https://github.com/namibj/BondTest72-Programmable-LDO GitHub - namibj/BondTest72-Programmable-LDO: MCP4725-based addon fo... MCP4725-based addon for BondTest72 r2, providing a programmable LDO and precision 3.0V reference - namibj/BondTest72-Programmable-LDO 2026-11_media/BondTest72-Programmable-LDO-F30EC [2026-11-01 11:33 a.m.] chips4makers The latest dev branch should work. ```console % uvx --refresh git+https://gitlab.com/Chips4Makers/c4m-arrakeen-memgen.git@dev This is project Arrakeen's memory generator. This is pre-alpha quality software; just above proof-of-concept level. Don't use it for production; no support is provided and use is at own risk! If it breaks you may keep the pieces. Select technologies: 1) IHP SG13G2 2) Sky130 3) GF180MCU ...``` [2026-11-01 11:34 a.m.] chips4makers 512 is max. number of words currently supported by the compiler. The decoder generation for bigger number of words is not implemented yet. [2026-11-01 12:35 p.m.] namibj I'm gonna draw up a 2L flex board using the JLC special (5pcs up to 100x100 2L 1/3oz thin PI core only no stiffeners no soldering); I'm currently planning to do a multi-opportunity breakout board that utilizes the 3 flip chip bond pad structures in various combinations/styles (there's 3 nets; 2 of the 3 structures only have one pad per net; the third structure has larger grid pads and offers each net twice and routed so that it's at most diagonally/corner adjacent not sidways to challenge bonding processes that may be prone to shorting out adjacent pins), wiring out the DUT nets to some sort of "connector" that an ohmmeter can then be connected to for testing bond quality. What kind of connector would you think I should go with there? Some kinda 4-wire ZIF style replicated around the outer border to hopefully cover all the DUT bonds so that a tester could be ZIF-connected to all of them in series to try them? Just a wider ZIF connector for like each DUT/bond site approximately and plan on using an external breakout from that to a pin header or such? Solder connections for attaching pin headers to the flex around the edge after the flip chip bonding has been done? Any opinions? @Essen @Lauri @Andrew Wingate ? [2026-11-01 12:47 p.m.] namibj Primary testing would be 4-wire measurements of nets through the bonds at both ends; where applicable isolation testing is also on the docket. Where there are more than 2 pads for each net bonded out (there are 4 pads on the die for each net, but most DUT bonding sites on the test flex won't have all of them), the results from pairwise 4-wire measurements ought to reveal per-bond resistance, though possibly it might require adding a third voltage measurement wire into it, I'm not sure off the top of my head. [2026-11-01 4:48 p.m.] namibj yeah works. I took a look at the decoder generation code and it seems `RowPreDecodersT` could be taught to handle `(address_groups[0] != 3)`, specifically, `(address_groups[0] == 4)`, for a straight forward one extra bit (so up to 1024 words), as well as an easy extension by allowing to layer another pre-decoder in front of the current pre-decoder, where the new pre-decoder would merely act on this new (optional) 4th input bit of the current pre-decoder stage. It'd have to spread them a bit more vertically I think to not get routing congestion at the current last level decoder/page pitch, but otherwise I think it should work? And like, without having to make the row periphery wider. Unless this would not possibly fit in the limited routing channels on the left side over the input DFFs; it does look quite tight there. On further look it does appear to be mighty tight already.... Seems like it'd still be worth it though, at least with a word size notably larger than the tiny 8 bit (so that the extra decoder column of row periphery space doesn't dominate). @Tholin How large of an SRAM would you _want_ to stick in that corner if you would get to wish anything the FlexMem compiler could support if it had sufficient demand to warrant the implementation/support effort? [2026-11-01 4:49 p.m.] tholin 4096 x 8 [2026-11-01 4:51 p.m.] tholin Actually, make that 8192 x 8 [2026-11-01 4:51 p.m.] tholin If possible [2026-11-01 4:51 p.m.] tholin Idk if that’d fit [2026-11-01 4:51 p.m.] tholin I don’t even know if 4096 would fit [2026-11-01 4:52 p.m.] namibj would you be happy with 512x64 with byte granularity write enable? [2026-11-01 4:53 p.m.] namibj single port, right? [2026-11-01 4:54 p.m.] tholin Yeah [2026-11-01 4:54 p.m.] namibj I'll generate the 512x64_8we first (oh, already done...), let's see how large it is. [2026-11-01 4:57 p.m.] namibj can you measure me the area allowance? [2026-11-01 4:58 p.m.] namibj this is 1102 wide and 246 tall [2026-11-01 4:59 p.m.] namibj 2167 wide [2026-11-01 5:03 p.m.] tholin I can do 2167 by 246 [2026-11-01 5:04 p.m.] namibj yeah the 512x64_8we should fit and actually you should be able to put 4 of them in horizontally I think..... [2026-11-01 5:05 p.m.] namibj have fun generating then! https://discord.com/channels/1361349522684510449/1361349523724570941/1566414975290056855 [2026-11-01 5:05 p.m.] tholin Yep. Two of them, and I can do a version of the AS2650v2 that does not require caravel. [2026-11-01 5:06 p.m.] namibj the external column mux would be a "little" hard I fear [2026-11-01 5:06 p.m.] namibj well, density on it [2026-11-01 5:08 p.m.] namibj future works (inbuilt multiplexer/decoder support for getting more desiable aspect ratios despite narrow requested access bus width) [2026-11-01 5:09 p.m.] tholin What’s "uvx"? [2026-11-01 5:10 p.m.] namibj due to the native width being "excessive", you could in theory even consider doing SECDEC ECC on it.... e.g. a 9th byte of width (72 instead of 64) is cheap there... the size would be in the coder, not the array. [2026-11-01 5:10 p.m.] namibj like npx but uv [2026-11-01 5:10 p.m.] namibj AFAIK [2026-11-01 5:10 p.m.] namibj you can also run from in the cloned repo [2026-11-01 5:11 p.m.] namibj if you ask what specific config I shall put in I can do it and send you a zip [2026-11-01 5:14 p.m.] tholin {Attachments} 2026-11_media/image-0A796.png [2026-11-01 5:14 p.m.] namibj welp 🙁 Feel free to tell me what config I'll generate it for you with the LEF and ngspice and verilog folders. [2026-11-01 5:16 p.m.] tholin It doesn't like the nix shell [2026-11-01 5:16 p.m.] namibj yeah I see [2026-11-01 5:17 p.m.] namibj @Tholin If you can, I'd appreciate some opinionated insight for the decision of how to "pin out" the group of flip chip DUT chips. [2026-11-01 5:19 p.m.] tholin The what? [2026-11-01 5:21 p.m.] tholin I’m not sure what useful input I could give on that [2026-11-01 5:24 p.m.] namibj The `FC01` dies, I'm doing a 100x100 mm outline flex pcb with several footprint variants for this; to be tested and afterwards measured for bond resistance (you can see the traces somewhat on the die; those allow measuring continuity and also confirming that no adjacent pads got shorted out in the bonding process). {Attachments} 2026-11_media/image-CDDD8.png [2026-11-01 5:26 p.m.] namibj I'm quite indecisive on the matter of 'what "connector footprint" to put around the edge(s) of the pcb to be convenient for subsequent measuring of whether the bonding attempts were successful'. [2026-11-01 6:33 p.m.] tholin I generated a 512x128 RAM and I believe I can fit it at the right hand side of the die [2026-11-01 6:33 p.m.] tholin Its actually almost a perfect fit height-wise [2026-11-01 6:41 p.m.] namibj hmmmm [2026-11-03 12:34 a.m.] tholin Can’t get the RAM to hook up to the PDN for some reason [2026-11-03 12:34 a.m.] tholin I don’t think it likes being rotated 90 degrees [2026-11-03 3:20 a.m.] namibj ensnare it in a macro power ring while rotated normally; then rotate it the 90 degrees? [2026-11-03 3:44 a.m.] velvetundergroundandy haha anyone have a microcontroller like chip on run 2? [2026-11-03 4:15 a.m.] namibj `HZ80` plus `DPK1` (the former Z80 clone bit banging firmware out of nonvolatile storage into the instruction memory of the bao IO controller thing (`DPK1`). ? [2026-11-03 4:15 a.m.] namibj https://github.com/wafer-space/ws-run2 check here {Embed} https://github.com/wafer-space/ws-run2 GitHub - wafer-space/ws-run2: wafer.space GF180MCU Run 2 wafer.space GF180MCU Run 2. Contribute to wafer-space/ws-run2 development by creating an account on GitHub. 2026-11_media/ws-run2-1AF31 [2026-11-03 4:22 a.m.] anfroholic @RebelMike has a number of them I believe. [2026-11-03 8:42 a.m.] rebelmike Yes, the run 2 version of TinyQV is along those lines: https://github.com/MichaelBell/ws02-tinyqv No dedicated I2C peripheral though potentially you could bit bang it {Embed} https://github.com/MichaelBell/ws02-tinyqv GitHub - MichaelBell/ws02-tinyQV: TinyQV for Wafer Space run 2 on g... TinyQV for Wafer Space run 2 on gf180mcuD. Contribute to MichaelBell/ws02-tinyQV development by creating an account on GitHub. 2026-11_media/ws02-tinyQV-824C7 [2026-11-03 4:38 p.m.] tholin https://discord.com/channels/1361349522684510449/1361349523724570938/1567027653540581488 [2026-11-03 4:38 p.m.] tholin Does this chip not contain layouts created using my SCL? [2026-11-03 4:38 p.m.] tholin @Andrew Wingate [2026-11-03 4:43 p.m.] anfroholic Correct (I think) This was tiny tapeout's experimental chip. Maybe @tnt could give some better insight. [2026-11-03 4:45 p.m.] 246tnt Not usable ones. [2026-11-03 4:47 p.m.] 246tnt We had released the final GDS before the `buf_8` fix so all the designs using that SCL are expected DOA. [2026-11-03 4:47 p.m.] tholin That’s not the case [2026-11-03 4:47 p.m.] tholin The buff_8 will still work, just with excessive power consumption when on [2026-11-03 4:48 p.m.] tholin One out of 8 transistors was shorted, and the remaining 7 are enough to power the short and still generate a clean logic level. [2026-11-03 4:48 p.m.] tholin Remember that this bug only got past me because the cell still passed SPICE simulation. [2026-11-03 4:49 p.m.] tholin (also its buff_8 not buf_8, I always hated the abbreviation of "buffer" with one "f") [2026-11-03 9:11 p.m.] velvetundergroundandy nice i'll talk to mike in DM's about it [2026-11-03 9:51 p.m.] velvetundergroundandy Were there also any RISC V micros in run 1 that people also have their hands on? [2026-11-03 10:53 p.m.] rebelmike I have a couple of TQVCs and have got them working [2026-11-03 10:55 p.m.] rebelmike TQVA-C are a straight port of the Tiny Tapeout design and so don't have full control over the IOs - the general purpose IO is split into 8 inputs and 8 outputs. That's fine for SPI but fairly terrible for I2C [2026-11-03 11:41 p.m.] velvetundergroundandy amazing! [2026-11-03 11:49 p.m.] tholin Magic has been taking a few hours on this one {Attachments} 2026-11_media/image-965A5.png [2026-11-03 11:49 p.m.] tholin Is there a bug that it can get into an infinite loop? [2026-11-03 11:51 p.m.] tholin I think I found a bug {Attachments} 2026-11_media/image-EE2BF.png {Reactions} 🤣 [2026-11-04 12:25 a.m.] mithro_ https://wafer.space/ws-run2 is probably a nicer to view version {Embed} https://wafer.space/ws-run2 wafer.space Run 2 — wafer.space Designs, density statistics and layout renders from wafer.space GF180MCU Run 2. 2026-11_media/reticle-81EC2.webp {Reactions} ❤️ [2026-11-04 12:26 a.m.] mithro_ @Paul - https://wafer.space/ws-run2/#cpus {Embed} https://wafer.space/ws-run2/ wafer.space Run 2 — wafer.space Designs, density statistics and layout renders from wafer.space GF180MCU Run 2. 2026-11_media/reticle-81EC2.webp [2026-11-04 12:26 a.m.] mithro_ @Paul - https://wafer.space/ws-run1/#cpus {Embed} https://wafer.space/ws-run1/ wafer.space Run 1 — wafer.space Designs, density statistics and layout renders from wafer.space GF180MCU Run 1. 2026-11_media/reticle-AC118.webp {Reactions} ❤️ [2026-11-04 9:48 a.m.] tholin Getting a TON of antenna violations around the RAM now that it seems to be unable to repair [2026-11-04 9:48 a.m.] tholin Using this RAM generator has been a pain so far {Reactions} 👍 (2) [2026-11-04 4:27 p.m.] chips4makers Why do you need magic for LEF generation ? The compiler should also generate lef files. [2026-11-04 4:30 p.m.] tholin I modified the GDS file to have Metal4 strips for the PDN to contact [2026-11-04 4:31 p.m.] tholin I may have to edit it more. Getting lots of antenna violations still and what can usually help is moving the macro ports to a higher metal layer. [2026-11-04 4:32 p.m.] tholin I doubt I’ll be able to insert diodes inside the RAM, so I hope that’ll be enough. [2026-11-04 4:39 p.m.] 246tnt Ideally you wouldn't be editing the GDS but wrapping it. [2026-11-04 4:52 p.m.] chips4makers Ideally OpenROAD should be able to handle the SRAM as is and do proper supply connection and antenna diode insertion. @Tholin Are you using librelane ? For my tape-outs @Leo Moser (mole99) helped me doing the tape-outs without needing to wrap the memory block. If I remember correctly for the half slot test chip the blocks were rotated also. It did contain minimal amount of logic though. [2026-11-04 4:54 p.m.] 246tnt I'm pretty sure it can. You need an appropriate `pdngen` configuration to tell it what to connect how. [2026-11-04 5:03 p.m.] tholin Idk how the Metal5 power straps could possibly connect to the RAM if it has no rails on Metal4 [2026-11-04 5:03 p.m.] tholin And indeed the PDN did not make any connections until I added those [2026-11-04 5:03 p.m.] tholin But right now I’m more concerned about the antenna violations [2026-11-04 5:12 p.m.] 246tnt pdn gen is perfectly capable to connect down from Met5 to lower metal, adding island and via stacks as needed. [2026-11-04 5:13 p.m.] 246tnt But that's not something it will just do with default config. [2026-11-04 7:18 p.m.] tholin The generated LEF file is missing antenna information, maybe that’s why librelane is struggling to pick up on the antenna violations. [2026-11-04 10:18 p.m.] tholin Under normal circumstances, I’d do a LEF write from magic and have it generate this data, but it still gets stuck in an infinite loop when I try. [2026-11-04 11:34 p.m.] tholin {Attachments} 2026-11_media/image-9DA29.png {Reactions} 😬 [2026-11-05 10:15 a.m.] mole99 @Tholin You can find the pdn setup here: https://gitlab.com/Chips4Makers/arrakeen-sram-testchip/-/blob/main/template/librelane/pdn/pdn_TestChip.tcl?ref_type=heads It's as simple as telling pdngen to connect Metal5 (PDN_HORIZONTAL_LAYER) and Metal3. {Embed} https://gitlab.com/Chips4Makers/arrakeen-sram-testchip/-/blob/main/template/librelane/pdn/pdn_TestChip.tcl?ref_type=heads template/librelane/pdn/pdn_TestChip.tcl · main · Chips4Makers / A... GitLab.com 2026-11_media/twitter_card-570ddb06edf56a2312253c5872489-60AF3.jpg [2026-11-05 10:17 a.m.] tholin I’m more concerned with the antenna errors [2026-11-05 10:18 a.m.] tholin I tried using insert ECO diodes to force diodes at all the RAM inputs and that made it *worse* [2026-11-05 10:21 a.m.] mole99 You can load the `.lyrdb` file into KLayout to see exactly where and why antenna violations exist. [2026-11-05 10:24 a.m.] tholin I did [2026-11-05 10:24 a.m.] tholin Its all around the RAM [2026-11-05 10:25 a.m.] tholin The RAM generator does not put any antenna gate area information in the LEF. [2026-11-05 10:25 a.m.] tholin LibreLane doesn’t even pick up on the fact that there are these violations [2026-11-05 10:34 a.m.] mole99 You could put some dummy antenna information in the LEF. And please open an issue at [c4m-flexmem](https://gitlab.com/Chips4Makers/c4m-flexmem) so Staf can keep it in mind. {Embed} https://gitlab.com/Chips4Makers/c4m-flexmem Chips4Makers / c4m-flexmem · GitLab A flexible, scalable memory generator. 2026-11_media/twitter_card-570ddb06edf56a2312253c5872489-60AF3.jpg [2026-11-06 1:41 a.m.] bailey8889 @Tholin different process, but this talks about adding diodes to sram inputs. https://discord.com/channels/1009193568256135208/1567679061235597363/1567898247991660565 [2026-11-06 9:34 a.m.] lothar_51730 Hi! I’m planning a mixed-signal design for the upcoming GF180MCU run using the gf180mcu-project-template (gf180mcuD). Before I start the analog blocks, I’d like to confirm which optional process modules are included: MIM capacitor: Is MIM available on this run? If so, which option (1.0, 1.5 or 2.0 fF/µm²), and is it between Metal4 and Metal5 as in the Magic tech file? High-Rs poly resistor: Is the optional high-sheet-resistance poly (ppolyf_u_1k / _2k / _3k, mask L63) included, or should I stick to the standard unsalicided poly (ppolyf_u / npolyf_u)? Thanks a lot! Wenn du willst, kann ich die Frage noch kürzer oder förmlicher machen, etwa für eine E-Mail statt Discord. [2026-11-06 1:28 p.m.] namibj Do we have any vaguely hard idea of the surface countour from a pad outwards? Or even in theory just around a pad? [2026-11-06 1:39 p.m.] namibj @InfoSecDJ that cross-section you did through the pads, would it be difficult for you to apply some focus stacking or whatever necessary to get a good understanding of how the top surface actually looks from a topography POV? I'm asking to hopefully be able to pick an appropriate ACF tape that won't necessitate applying plating on the die to build the natural pad up into a true raised bump that reaches above the passivation's height. [2026-11-06 1:42 p.m.] infosecdj the link below there is actually focus-stacked. see if that helps, and although passivation oxide is naturally invisible there, you can kinda infer where it ends -- that's where all the junk stuck in PI begins. looks quite a bit above the pad metal. [2026-11-06 1:45 p.m.] infosecdj 🤷 at least that's how I interpret the visuals there, I might be wrong on that [2026-11-06 1:46 p.m.] namibj https://infosecdj.net/map/wafer-space/gf180mcu-ws1-xs1/infosecdj_nikpa100ncg/#x=11273&y=1053&z=6 Is it about this recess (I cut off the other side to the right to maintain this zoom level)? {Attachments} 2026-11_media/image-6CEC0.png [2026-11-06 1:47 p.m.] namibj {Attachments} 2026-11_media/2_cross_section_39-E5CE9.png [2026-11-06 1:47 p.m.] namibj {Attachments} 2026-11_media/pad2-6C88D.png [2026-11-06 1:52 p.m.] namibj .....what direction to the pad frame was the image plane oriented, and while the die-thickness-reference and what's face of the die and what's backside-of-die are obvious, I'd like to have somewhat confirmed what's the right/left edge of the image region. [2026-11-06 1:59 p.m.] 246tnt On the right side is the corner of the pad frame. All the little square between the two pads are the fill pattern between the bond pads. [2026-11-06 2:02 p.m.] infosecdj https://infosecdj.net/map/wafer-space/gf180mcu-ws1-gd03/infosecdj_mz_nikpa40x/#x=4518&y=62416&z=4 {Attachments} 2026-11_media/image-C6D77.png [2026-11-06 2:04 p.m.] namibj {Attachments} 2026-11_media/SCRIBE_LINE2-FCFFC.png 2026-11_media/screencapture-gf180mcu-pdk-readthedocs-io--28375.png [2026-11-06 2:05 p.m.] namibj If I measure at the right edge I do indeed measure that "pad opening" to be the DRC spec "wire bond"-class sealring's "pad opening". [2026-11-06 2:09 p.m.] namibj ahhh hmmm [2026-11-06 2:12 p.m.] namibj @tnt Do you think that perhaps using some polishing/flattening technique to get rid of the currently-raised ....**_polyimide?_** down to the height of the aluminium pads would _work?_ [2026-11-06 2:17 p.m.] 246tnt Seems unlikely ... maybe some special solvant ... [2026-11-06 2:19 p.m.] infosecdj polyimide is, unfortunately, very resistant to solvents I know of. in fact, removing polyimide before imaging has proven to be a challenge for me here, as nothing I am able to obtain can do anything about it. so either heat or aggressive chem, neither of which is a good approach. [2026-11-06 2:21 p.m.] 246tnt Monoethanolamine ... good luck finding some 😅 [2026-11-06 2:24 p.m.] infosecdj does it actually work? is it worth the hassle of hunting for sources? [2026-11-06 2:26 p.m.] namibj Oh I meant in a sense of planarization. [2026-11-06 2:28 p.m.] 246tnt https://patentimages.storage.googleapis.com/57/b1/0f/1a678067b52dd4/US6319884B2.pdf Seems to work when mixed with some other one. There are dedicated solvants to it seems (made specifically for the Silicon industry), but those are probably harder to track down, although maybe @azonenberg knows where to get that kind of stuff ? [2026-11-06 2:28 p.m.] namibj In theory the easier treatment would be to run a zincate-ENIG plating though I don't think the "final" gold layer is as important for ACF tape as it is for soldering. [2026-11-06 2:31 p.m.] namibj I'm just rather poorly suited to do such properly, not alone because it sounds like it'd realistically involve nitric acid at around half of the regular non-fuming concentrate strength (i.e., 30 ish percent), and I recall concentrated nitric acid to be fairly regulated in and around Germany. [2026-11-06 2:33 p.m.] infosecdj you'd be very right on that. [2026-11-06 2:39 p.m.] azonenberg Concentrated sulfuric (at very elevated temps) or various oxygen/fluorine based plasmas are the usual options [2026-11-06 2:41 p.m.] 246tnt @azonenberg But wouldn't that attack the Aluminium too ? [2026-11-06 2:42 p.m.] azonenberg Not significantly, at least for the duration you need to get the polyimide off [2026-11-06 2:42 p.m.] azonenberg at least that's been my experience [2026-11-06 2:43 p.m.] azonenberg Backing up a bit: what is the overall goal? [2026-11-06 2:43 p.m.] azonenberg there will be overglass above the edge of the aluminum even if you remove the PI [2026-11-06 2:43 p.m.] namibj I guess there's hoping the pad thickness of around 4.5um and the passivation bump/buffer around it suffice to keep the 11um (c.f. stackup; the coverlay is pulled back around the relevant area anyways) copper traces that intersect the pads at the padframe and are otherwise aimed/oriented to escape from the die for now (there'll be tests to qualify an opportunity for future TinyTapeout to support direct pads over user tiles set up such that realistically a minimum analog project could hold 2 pads and an analog mux spine could sustain this, but there'd need to be probably at least one digital spine between two analog ones (vertical pitch) and if packing the die with this, there'd probably need to be two distinct flip-chip-fan-out setups where any given die can only support _either_ the even-rows _or_ the odd-rows of counting only analog spines). {Attachments} 2026-11_media/img_1d2b4fa5-1E953.png [2026-11-06 2:44 p.m.] namibj Do you know how ACF tape interacts with surface topography of both sides in a face-bonding application? [2026-11-06 2:45 p.m.] azonenberg how large are the filler particles in your tape? [2026-11-06 2:45 p.m.] azonenberg i would expect "normal" ACF to be far too large particles/pitch [2026-11-06 2:47 p.m.] azonenberg Like 3M 7303 is 43um particles and wants a 250um pitch [2026-11-06 2:47 p.m.] azonenberg which is far bigger than a bond pad [2026-11-06 2:47 p.m.] azonenberg i assume you can get smaller pitch stuff for COB/COF applications but i dont have specs for how much [2026-11-06 2:56 p.m.] namibj I'm expecting "the fine stuff" that can realistically replace "classic" wafer level BGA-bumping for attaching to fine-pitch substrates. Like, the fine pitch stuffs that adapts from on the order of 100um pitch to 0.4~1mm BGA pitch as you may find in packages with multiple hundreds of balls. [2026-11-06 2:58 p.m.] namibj https://www.resonac.com/products/semi-backend-process/77/001.html their AC-10000 series is Minimum contact area 3000 μm2 (which I incidentally match exactly) and MInimum Space 10 μm. {Embed} https://www.resonac.com/products/semi-backend-process/77/001.html ACF (Anisotropic Conductive Film) for Film Substrate Connections​... Resonac’s ACF connects film substrates, such as FPC and COF, to display panels. Resonac pioneered this film material that combines thermosetting resins and conductive particles to achieve both conductive and insulative properties. 2026-11_media/img-pickup-default-01-81FF5.png [2026-11-06 3:05 p.m.] azonenberg but no information on planarity requirement? does it list the sphere size? [2026-11-06 4:53 p.m.] namibj not directly, at least without "inquiry". As for planarity, well, it's generally a complex topic, due to how it interacts when manufacturing stuff. [2026-11-06 5:02 p.m.] namibj I had found a paper that did a test die they plated copper pillars onto and pushed face bonding rectangular array pad pitch substantially beyond what we could reasonably hope for on our stuff, at least without finding an MPW source for cheap silicon interposers or doing cursed stuff with face-to-face bonding of gf180mcuD dies (imagine face-bonding a half-height slot stuffed with SRAM and not having a bond pad ring, right over the core area of a full slot that otherwise gets "regular" COB wire bonding, to attach a comfy amount of fast RAM (_very_ many pins possible, and no need for remotely bulky drivers due to inherently small capacitances) to something like a "normal" microcontroller or other general purpose ASIC). Edit: yeah, like maybe 128 kiB or a bit less could probably fit, I guess... [2026-11-06 5:03 p.m.] namibj I'll have to get outside and take care of some stuff while places are still open, and will see to grab the paper and whatever ACF nuances it iirc mentioned/detailed when I'm back home. [2026-11-06 5:28 p.m.] namibj @azonenberg here, the paper: they did 55μm pitch with the following: >>> The bumps obtained were 6 µm high above the pad, with a diameter of 19 µm. For the flip-chip hybridisation, an ACF of 18 µm thickness containing 3 µm-diameter nickel- coated conductive particles (CP) with a density of 71,200 CP/mm² was used. The ACF was laminated on the Ti-LGAD sensors at 90 °C under a pressure of 3.2 kgf (Fig. 1b), followed by bonding at 160 °C under 20 kgf for 2 s using a SET ACCµRA100 flip-chip bonder [7]. [2026-11-06 5:31 p.m.] namibj Excluding the weak center they attribute to vacuum grooves in the bonder head used (they could have done without the grooves but didn't have such a head ready/on hand), they got 99.5% well-connected bonds [2026-11-06 5:40 p.m.] namibj {Attachments} 2026-11_media/Screenshot_2026-11-06-18-39-07-77_e2d5b3f3-046F1.jpg [2026-11-06 5:42 p.m.] namibj (for the record, we're aiming at like 30μm x 30μm pads at the small end, not 19μm diameter circles) [2026-11-07 7:57 p.m.] tholin DRC and Antenna clean {Attachments} 2026-11_media/chip_top-A3F48.png {Reactions} 🔥 (6) [2026-11-07 11:33 p.m.] tholin Ready to receive my COBs {Attachments} 2026-11_media/20261108_003250-DC9CD.jpg {Reactions} 🔥 (3) 💯 (2) 💜 [2026-11-08 4:03 p.m.] archit3ch has anyone tested their 3/2/1 sided pad rings from run 2? 🥺 [2026-11-08 5:50 p.m.] essen__ I don't think anyone in the community has manufactured such padrings yet. [2026-11-08 5:52 p.m.] mole99 Actually, LibreLane allows you to remove sides from the padring :) See Mike's TQVE: https://github.com/wafer-space/ws-run2 [2026-11-08 9:29 p.m.] rebelmike I should make a motherboard for TQVD, and a CoB board for TQVE so we can test that out! [2026-11-08 10:37 p.m.] alexp122 Can someone help me how layout this in Klayout please it would be pretty helpful. Thanks {Attachments} 2026-11_media/Screenshot_2026-11-08_143150-5749C.png [2026-11-08 10:49 p.m.] alexp122 My friend and I are working on this project and have zero experience with Klayout. If anyone can help would be grateful. [2026-11-09 1:59 a.m.] essen__ This will not be the right community for getting help if you have zero experience. But the analog threads on Tiny Tapeout will be a better resource for you. [2026-11-09 2:01 a.m.] alexp122 Okey thank you for the help. [2026-11-09 6:58 a.m.] 246tnt You might want to check stability. A two stage op-amp without compensation could oscillate. [2026-11-09 2:16 p.m.] 246tnt Has anyone started testing of run#2 chips ? {Reactions} 👀 (2) [2026-11-09 3:36 p.m.] anfroholic Other than the small test we did, you are the first to receive any chips afaiu [2026-11-09 4:25 p.m.] 246tnt 😬 [2026-11-09 4:25 p.m.] 246tnt Is the COB being done for the others currently ? [2026-11-09 5:51 p.m.] namibj do tell what chips you got to try! ttgf0p3? [2026-11-09 5:51 p.m.] namibj (I thought that was a different COB base underneath?) [2026-11-09 5:56 p.m.] 246tnt Yes, `ttgf0p3` assembled on a standard wafer.space breakout. Most TT chips will be bonded on a custom breakout that directly goes to our standard demo board, but the padframe is compatible with wafer.space COB so a few chips were mounted to it and I got a few samples. [2026-11-09 6:40 p.m.] namibj ahhh I see. well, that LDO Add-On you AFAIK have gives you a fairly strong buffered DAC feed on `COME` if plugged in; it should suffice to e.g. read the ROM tile; unfortunately for this your reception of the gear was a surprise event to me; I didn't think anyone would actually have stuff they'd may wanna use the DAC Add-On for/with for at least the next several days..... [2026-11-09 6:42 p.m.] namibj oh reading helps; you've already connected it to a testbench driver setup of some sort given the reports made. [2026-11-09 6:43 p.m.] 246tnt I have a converter that allows me to connect those COB to the TT devboard, easier for testing 😅 {Reactions} 👀 [2026-11-09 7:29 p.m.] namibj fair. I just checked and mathed some and I _think_ the short of `ua[1]` to `VSS` on https://tinytapeout.com/chips/ttgf0p3/tt_um_mcml_vco could be electromigrated away over the course of hours to maybe a couple days (seems to mostly depend on how close to melting fuse in seconds one wants to push the trace).... Do you think the MUX will cope with some 10~40 (ish) mA into a fairly low resistance short to VSS (should be less than 5 Ohm I'd guess, at least for anything within the tile)? {Embed} https://tinytapeout.com/chips/ttgf0p3/tt_um_mcml_vco 454 MCML VCO - Tiny Tapeout An MCML VCO 2026-11_media/social-preview-9F844 [2026-11-09 7:30 p.m.] 246tnt huh, out of 6 samples, I have 2 working ones, so I'm not trying anything crazy 😅 [2026-11-09 7:31 p.m.] namibj oh no I wasn't suggesting you try anything like that with your precious frist wafer lot's first COB batch 😄 [2026-11-09 7:53 p.m.] namibj also the thing has only 12 `via3`'s to the `VSS` LEF pin :/ [2026-11-10 12:19 a.m.] tholin I added a xor3 cell to my SCL, which was long overdue. This should help generate more efficient adders and thus improve the most common critical paths. {Reactions} 👏 [2026-11-10 5:15 a.m.] saladchap Yes, chips and boards are with the bond house now ============================================================== Exported 180 message(s) ==============================================================